先進封裝的廣闊視野—對話長電科技首席技術長李春興

時間：2022/01/13    點擊量：437

“先進封裝技術因其在延續摩爾定律，促進芯片性能提升方面的重要價值，近來成為IDM與OSAT企業共同關注的焦點。隨著技術演進，各應用領域對采用先進封裝的芯片成品，也呈現出多元化需求。”

作為從業者，會如何看待先進封裝的發展趨勢？對不同先進封裝技術的現狀和發展又有怎樣的見解？日前，長電科技首席技術長李春興（Lee Choon Heung）先生，與美國Semiconductor Engineering網站進行了一次涉及半導體市場前景、摩爾定律、小芯片（Chiplet）、扇出型封裝（Fan-out）等市場與行業熱點的對話。

李春興  Lee Choon Heung

李春興博士自2019年5月17日起出任長電科技首席技術長，擁有美國凱斯西儲大學理論固體物理博士學位。

李春興博士在半導體領域擁有20多年的工作經驗，曾任Amkor Technology首席技術官、全球制造業務執行副總裁和Amkor韓國總裁。李博士撰寫有各種封裝技術相關課題的研究論文，擁有韓國專利38項，美國專利21項。

以下為對話摘錄（SE=Semiconductor Engineering）：

SE：我們現在處于半導體周期的哪個階段？

李春興：2020 年整個半導體行業的增長率約為10%。到2021年，預計將增長將達到24%左右。今年較高的增長可以歸因于新冠疫情的影響——大家都在購買各種電子設備，保持與外界的連接。如果對2022年做個預測，增長率可能只有個位數字。盡管如此，就半導體復合年增長率或CAGR而言，不考慮通貨膨脹或其它因素，只是看半導體市場本身，這個（增長）仍然是很穩定的。只有2021年比較特殊。

Lee: If you look at 2020, it was around 10% growth in the overall semiconductor industry. Then, in 2021, it is expected to be about 24% growth. This can be attributed to the Covid situation. Everyone is buying all types of systems to connect with each other. But if you look at 2022, it looks like single-digit kind of numbers. Still, in terms of the semiconductor compound annual growth rate, or CAGR, it looks solid. It’s just that 2021 is really exceptional. I’m not taking in account the other parameters like inflation or other factors. If you look at the pure semiconductor market, it looks okay.

SE：芯片市場有哪些主要驅動因素？

李春興：汽車行業是推動力之一。盡管存在芯片短缺，但汽車行業仍在增長，電動汽車、自動駕駛等正在推動（芯片市場）增長。現在汽車行業一直關注安全性，與安全相關的功能，例如傳感器或者高級駕駛輔助系統（Advanced Driving Assistance System, ADAS），都是芯片在汽車行業應用增長的推動力。許多汽車產品中，每輛車的電子設備費用達到600美元，而且汽車中的電子設備還將增加。然后還有5G相關應用，比如“車與車”交互，這推動了高端信息應用市場。這些技術現在仍處于早期階段，不過每個汽車制造商都在關注這一領域。

Lee: Automotive is one of the driving forces. Even though there are chip shortages here, automotive is still growing. Then, electric vehicles, autonomous driving and so on are fueling the growth. And for some time, the automotive industry has been focusing on safety. You have safety-related features in cars like sensors or even ADAS. That’s a big driver in automotive. The electronic content in many cars is around \$600 per car. It’s going up from there. Electronic content in cars will increase. Then, for 5G-related applications, you have car-to-car or vehicle-to-vehicle (V2V) communications. That’s driving the high-end infotainment market. This technology is still in the early stages. Every carmaker is looking at that.

SE：還有什么在推動半導體市場，對封裝有什么影響？

李春興：另一個驅動因素是人工智能。人工智能涉及高性能計算（HPC）。我們看到與AI或HPC應用相關的FcBGA需求很大。這其中還包括2.5D、3D或高密度扇出型封裝產品。云計算是人工智能應用的一個大市場，數據中心行業的需求持續提高，他們需要更好的產品以提高效率并降低運營成本。這部分的市場規模正在以驚人的速度增長。

Lee: Another driver is AI. AI involves high-performance computing (HPC). We are seeing a lot of demand for flip-chip BGA, which is linked to AI or HPC applications. That also includes 2.5D, 3D, or high-density fan-out. The cloud is a big market for AI. The adoption rate here in data centers continues to increase. Data centers are also enhancing their efficiency and reducing their operational costs. The amount of data is increasing at a tremendous rate.

SE：那 5G 呢？

李春興：5G是通信領域的重要部分，但5G尚處于早期階段，還沒有進入成熟階段。由于新冠疫情，一些國家推遲或放慢了5G的基礎設施建設，預計明年5G基礎設施建設將提速。手機制造商也非常重視將5G功能納入其智能手機產品。對于OSAT企業，5G是一個很大的驅動力，我們也一直在為5G應用部署相關生產設施，尤其是系統級封裝（SiP）。另外5G還涉及AiP——即封裝天線這種新型的封裝技術。

Lee: In the communication sector, there is 5G. But 5G is not in the mature stages yet. It’s still in the early stages. Because of the Covid situation, some countries delayed or slowed their infrastructure buildouts of 5G. Next year, many will focus on bringing up the infrastructure in 5G. Every phone maker is serious about incorporating 5G content in their smartphones. For the OSAT market, 5G is a big driver. We have been expanding our capacity and putting the infrastructure in place for 5G demand, especially for system-in-package (SiP). In 5G, you also have AiP, or antenna-in-package, as a new feature in a package.

SE：您如何看待摩爾定律？

李春興：摩爾定律所說的“芯片密度每兩年翻一倍”這種情況很難繼續發生了，它并不是徹底失效，但正在放緩。

Lee: Moore’s Law, by definition, involves doubling the chip density every two years. But that isn’t happening anymore. It’s slowing down. But we can look at this from a different aspect. We’ve heard about a 40% performance increase at each node. But in terms of its original definition, Moore’s Law isn’t really catching up. It’s not really dead. It is slowing down.

SE：此時此刻一些傳統的技術正在蓬勃發展。成熟的200mm晶圓需求很大，是這樣嗎？

李春興：說起來很神奇，即使在OSAT中，8英寸晶圓級的需求也是巨大的，在某些情況下還要大于12英寸。正如我們所討論的，汽車行業是這里的一個重要驅動因素，另外還有工業物聯網，他們對模擬器件的需求是巨大的。在涉及電動汽車等技術時，功率變得越來越重要。

Lee: It’s amazing. Even in the OSATs, the 8-inch wafer-level demand is huge. In some cases, it’s bigger than 12-inch. It’s an inflection of the industrial transformation. As we discussed, automotive is a big driver here. Then, we have industrial IoT. Demand for analog is huge, even in automotive. Power is becoming more critical when it comes to technologies like electric vehicles.

SE：芯片封裝并不是新事物，但幾年前它比較邊緣，只是封裝和保護芯片。然而最近封裝在所有行業中變得越來越重要。發生了什么變化？

李春興：智能手機市場推動了最初的變化。智能手機中嵌入了更多的功能，如果觀察3G、4G和5G的演進，就會發現智能手機在同一主板區域內集成了更多芯片，對SiP封裝的需求越來越多。隨著從3G到4G以及從4G到5G的演進，芯片的大小尺寸（長、寬、高）成為智能手機的關鍵參數。另一個驅動因素是高性能計算領域。在先進封封裝中，扇出型封裝和RDL技術成為封裝模式中的基準。

Lee: The smartphone market drove some of the first changes. In a sense, there are more functions embedded in smartphones. If you look at the 3G, 4G, and 5G evolution, the smartphone incorporates more dies in the same motherboard area. That drove everything toward a SiP-type of format. The x, y, and z form factor became a critical parameter for the smartphone, along with evolution from 3G to 4G and 4G to 5G. Another driver is the high-performance computing area. Then, with (TSMC’s) InFO, RDL technology became a baseline for a packaging format in advanced packaging.

SE：小芯片（Chiplets）是一個熱門話題，因為它可以從模塊化功能中進行選擇。您對此怎么看？

李春興：很多人都在談論小芯片。在小芯片出現之前，人們就在想：“我希望在封裝架構中擁有不同功能的SoC，而不是傳統的單片 SoC。”這是影響封裝發展的一個變化。從某種意義上說，這種先進的封裝，或先進的產品需要高密度互連。因此，在這種情況下，封裝本身不再只是封裝單個芯片。在更先進的封裝中，必須考慮布局、芯片和封裝的互聯以及如何布線。這些正在成為元件制造商設計芯片時要考慮的一些基本參數。小芯片封裝現已進入市場。這個概念原先來自IDM或元件制造商——他們將封裝視為產品性能的一部分。

Lee: Everyone is talking about chiplets. Even before chiplets, people were thinking, ‘I would like to have a different and functional SoC in a package-like architecture instead of a traditional monolithic SoC.’ That’s another change that impacts packaging. In a sense, this kind of advanced package, or advanced product, requires high-density interconnects. So in that context, packaging itself is no longer just a single die in a package with encapsulation. In more advanced packaging, you have to think about the layout, the interactions with the chip and the package, and how to route these layers. These are becoming some of the fundamental parameters to think about when device makers design their own chips. Chiplets are already in the market. This concept is coming from the IDMs or the device makers. They look at the package as part of their product performance and product launch.

SE：能再多談論一些您對小芯片的看法嗎？

李春興：從系統的角度來看，Chiplet是一種多芯片架構。從OSAT的角度來看，問題在于如何真正在封裝中優化布局以獲得更佳性能。在某些方面，小芯片概念是由元件制造商去定義的，他們設想了拆分SoC的想法。模擬(器件)可能是一個節點。當制造商擁有16nm/14nm/7nm的IP時，需要進一步探索的問題在于如何獲得更好的晶圓產量并節省費用。總之從業者正在考慮如何從單片SoC設計中融入多種功能。

Lee: From a system point of view, a chiplet is a multi-die architecture. From an OSAT’s perspective, the question is how do you really optimize the layout to get the optimal performance or maximum performance in the package. In some respects, the definition of a chiplet is being driven by the device makers. The device guys envision the idea of breaking up an SoC. Analog would be at one node. Then, you might have 16/14nm/7nm IP. The argument is you get better wafer yield and save money. They are thinking about how to disaggregate the discrete functions out of a monolithic SoC design. Right now, AMD is very active in chiplets. They are working with TSMC on SoIC. They have already implemented this architecture and made improvements to the performance. AMD has fully utilized this advanced packaging concept.

SE：2015年，長電科技收購了星科金朋。現在長電科技能提供豐富的封裝和技術服務組合，業務遍及全球。接下來有什么計劃？

李春興：長電科技管理層已經提出了未來幾年的投入規劃。作為OSAT的領先企業，我們會對技術和制造能力進行持續投入。

Lee: We have an expansion plan. JCET management has approved a sizable CapEx for the years to come, and we have prepared the space in order to expand the capacity. As a leading figure in the OSAT market, we rely on the continuous investment in technology and manufacturing capacity.

SE：我們已經看到很多晶圓廠擴大了他們的封裝生產能力，例如英特爾、臺積電和三星。您對此怎么看？

李春興：在很多方面，晶圓廠更關注先進的封裝形式，這是晶圓廠的前端流程。我們也會專注于自身所長，晶圓級扇出封裝就是一個例子。我們正致力于2μm x 2μm線間距的技術開發，從而獲得更高性能和更高良率。

Lee: In many ways, the foundries focus more on advanced packaging formats, something like SoIC from TSMC. That’s a foundry front-end process. We want to focus on our own capabilities. Wafer-level fan-out packaging is an example. We are working on 2μm x 2μm with high performance and good yields.

SE：讓我們談談其它封裝類型，比如焊線。這仍然是一項大生意對吧？

李春興：就半導體的產量而言，焊線（封裝）約占80%。我們可以看看焊線封裝技術的演變，在我們的工廠中，我們可以處理一個芯片中包含2,500根焊線的封裝。焊線的優勢在于成本和可靠性，引線框封裝（Leadframe-based）及LGA封裝的價格比較低廉，它的需求量很大，我們也投入很多資源來擴大這類產能。

Lee: In terms of the number of units in semiconductors, wire bonding takes up like 80%. Take a look at the evolution at wire bonding technology. In our factory, we’re handling something like 2,500 wires in a package. One factor in wire bonding is cost. The other one is reliability. Leadframe-based or LGA packages are inexpensive. It’s a two-layer organic substrate. But it’s a huge number of units. We have spent a lot of money to expand the capacity here.

SE：扇出式封裝越來越受歡迎，長電科技對這種技術并不陌生。你們在嵌入式晶圓級球柵陣列（eWLB）有豐富的經驗對嗎？

李春興：長電科技的新加坡工廠是早期的eWLB封裝的參與者之一。我們從一開始就使用英飛凌的許可啟動了eWLB。扇出是一個分散的細分市場，我們也正在嘗試進入不同的細分市場。eWLB適合小批量、多元化的市場，在性能表現方面也很有價值，且具有封裝尺寸小的優勢。我們仍在關注eWLB市場的增長趨勢。

Lee: JCET’s Singapore operation was one of the early entrants in eWLB. They started eWLB from the very beginning with a license from Infineon. But fan-out is a fragmented market segment. We are trying to go into different market segments here. It’s a good fit for the low-volume, high-mix market, but it’s still valuable in terms of performance. It has some advantages with its x, y, and z form factors. Right now, we see the growth in eWLB. That’s the low-end of fan-out.

SE：長電科技最近憑借一項名為XDFOI?的技術進入了高密度扇出市場。能否介紹一下？

李春興：長電科技在今年發布了XDFOI?。這基本上是一種RDL優先，高密度扇出技術。我們正在開發具有2μm線寬和間距的RDL。相比之下，eWLB是10μm/15μm的線寬和間距。我們正在進入高密度扇出市場，為客戶提供新的選擇。許多人都看到了不需要硅中介層的扇出型封裝的價值。因此，長電科技計劃為客戶提供這種高端扇出產品。

Lee: JCET recently announced plans with XDFOI. This is basically a chip-last, RDL-first, high-density fan-out technology. We are developing RDLs with 2μm line and space. In contrast, eWLB is 10μm/15μm line and space. We are moving into the high-density fan-out market to provide new options for customers. Many see a value proposition using fan-out without the silicon interposer. So we plan to have a high-end fan-out offering from JCET.

SE：一些公司正在提供可以支持高帶寬內存（HBM）內存和其它復雜元件的高密度扇出產品，您對此怎么看？

李春興：當然，我們也有需要不同內存配置的高密度扇出產品的客戶。

Lee: Definitely, we have customers for our high-density fan-out with different memory configurations.

SE：高密度封裝的線間距是怎樣的趨勢？

李春興：目前，4μm x 4μm線間距已經量產（HVM），2μm x 2μm線間距也正在向量產邁進。雖然步進式光刻機可以處理1μm x 1μm線間距，但量產良率仍存在挑戰。如果不能解決量產良率，就沒有任何價值，所以我們還是更關注高良率。相比之下，采用四層RDL和2μm x 2μm線間距，良率要高得多。

Lee: Right now, 4μm x 4μm is used in high-volume manufacturing (HVM), and 2μm by 2μm is moving to HVM. In regard to the resolutions, steppers can handle 1μm x 1μm. But the challenge is to achieve the yields. Without achieving the yields, there is no value at all. Our focus is to achieve high yield. High yields translate well above 99% with a four-layer RDL and a 2μm line and space.

SE：你們的光刻流程是使用傳統步進式光刻機還是直寫式？

李春興：我們使用步進式光刻機。我們正在使用先進的系統，可以處理2μm x 2μm線間距。

Lee: We use the conventional stepper. We are using an advanced system. We can do 2μm x 2μm.

SE：扇出的最大挑戰是芯片移位和翹曲，對嗎？

李春興：在2umx2um線間距這樣的尺寸下，芯片移位并不是主要問題。當達到這么高的集成度時，particle才是最大的挑戰。

Lee: Die shift isn’t really the major issue in 2μm x 2μm. When you go down to these fine lines and spaces, particles are the killer in the process. Particles are the biggest challenge.

SE：這意味著您需要更多的檢查手段？

李：沒錯。在像10μm線間距這樣普通RDL中，底切是1μm。但到了2μm，底切是一個很大的挑戰。對比10μm x 10μm與2μm x 2μm，挑戰性完全不同。因此，需要非常謹慎地對過程進行優化。

Lee: Exactly. In normal RDLs like 10μm line and space, the undercut is 1μm. If you have 2μm line and space, the undercut is a big challenge. It’s a totally different challenge when you compare 10μm x 10μm versus 2μm x 2μm. So you need to be very cautious about fine tuning the process.

SE：您對面板形式的扇出（panel-level fan-out）有何看法？

李：四五年前我并不樂觀。問題出在面板格式方面沒有標準，設備也不夠成熟。今天這方面的驅動力又來自哪里？面板形式封裝要與晶圓級做對比——我不是在談論市場本身，也不是在談論哪些客戶會采用它。從成本的角度來看，如果一條12英寸線已經折舊了，你想開啟一個面板生產線，就必須考慮折舊問題。然后，新產品導入時，需要在面板上進行完整的認證，這是一種不同于晶圓級的調試過程。在一次會議上，我對晶圓級與面板級進行了比較。以7μm x 7μm的編解碼芯片為例，假設智能手機的銷量約為14億部，那么就需要14億個此類封裝。那么假設你擁有每月生產20,000個面板的產能，而只需要10,000平方米的面板就可以支撐這14億個產品。

Lee: Four or five years ago, I was very pessimistic. The issue is that there are no standards in terms of panel formats. At the time, there were equipment issues. There was a lack of maturity there. What’s the driving force today? The motivation of panel-level processing was cost compared wafer level. I’m not talking about the market itself, or which customers will adopt it. From the cost standpoint, a 12-inch line is already depreciated. If you want to start a panel line, you have to think about depreciation. That’s one issue. Then, whenever you have a new device, you need to undergo a full qualification process on panel. It’s a different qualification process from a wafer-level one. In one conference, I made the comparison between wafer-level versus panel-level. Take a codec-like chip at 7μm x 7μm, for example. Let’s say smartphone sales are roughly 1.4 billion. You need 1.4 billion units of this package for each phone as one example. Then, you might have a facility with 20,000 panels per month. Even a 10,000 square meter panel can handle 1.4 billion units.

SE：您對混合鍵合有什么想法？

李春興：混合鍵合在我們的計劃藍圖里，這與凸塊技術有關。索尼一直在使用混合鍵合，將之用于CMOS圖像傳感器。現在，很多人都在研究混合鍵合，它可以實現高密度的芯片到芯片鍵合，基本上是銅對銅的粘合。在混合鍵合中，不用銅凸塊上加入銀錫合金罩，它只是銅對銅，晶圓對晶圓鍵合的另一種互連過程。

Lee: We have hybrid bonding on the roadmap. This has something to do with the bump pitch. Sony has been using hybrid bonding. Sony has been doing this a long time for CMOS image sensors. Now, everyone is working on hybrid bonding. It enables high-density die-to-die bonding. It’s basically copper-to-copper bonding. In hybrid bonding, you are not extending copper bumps, which consists of a tin-silver cap on copper. It’s just copper-to-copper. It’s a different interconnection process of wafer-to-wafer bonding.

SE：在現在的先進封裝中，芯片使用銅微凸塊堆疊和粘合。最先進的微凸塊采用40μm間距，相當于20μm至25μm凸塊尺寸，管芯上相鄰凸塊之間的間距為15μm。業界正在致力于開發超過40μm的更細間距，以實現更多 I/O。您對此怎么看？

李春興：現在，40μm是量產中的常見凸塊間距。我們也正在致力于10μm，嘗試在這方面建立我們的工程數據。如果客戶希望他們產品的芯片到芯片鍵合間距降低到10μm，我們也能夠處理。但是當涉及到小于1μm的間距時，就會變得非常有挑戰性。通常這個挑戰會由晶圓廠去應對。一般來說OSAT的能力就只到10μm。

Lee: Now, 40μm is the common bump pitch for HVM. For 10μm, we are working on that. We are trying to build up our engineering data here. If customers want to go down to 10μm pitches for their own devices that involves die-to-die bonding, we will be capable of handling this. But when it comes to less than 1μm-like pitch, this is where it gets challenging. This is a foundry-like process. Generally, the capabilities for OSATs is down to 10μm, maybe past that pitch.

SE：您有關注熱壓粘合嗎？

李春興：沒有。我們實際上是采用激光輔助鍵合（LAB）。LAB將激光束照射到芯片上，其中凸點尖端是Sn或SnAg，用于將它們連接到基板。這提供了比熱壓更高的UPH（每小時產出）和更強大的互連，它的殘余應力比回流焊（MR）小得多。

Lee: No. We actually are employing laser-assisted bonding (LAB) instead. Laser-assisted bonding shines a laser beam to the chips, where the bump tips are Sn or SnAg. LAB is used to connect them to the substrate. This gives a higher UPH (units per hour) and more robust interconnection than thermocompression. It provides much less residual stress than MR (mass reflow).

SE：最后，有什么讓你非常擔心的事嗎？

李春興：在某些情況下，OSAT與晶圓廠在封裝技術上會有重疊，這使得OSAT的業務在投資支出和投資回報率方面有更多不確定性，另外也包括購置自動化專用的制造基礎設施時也可能出現競爭。

Lee: In some cases, packaging technologies often overlapped with the foundries in terms of capabilities, making the business situation more dynamic in the OSAT environment in terms of CapEx investment and ROI, as well as having a dedicated manufacturing infrastructure with automation.

圖文來源：中電網